Maestro Project
Maestro Project
The cluster computing has become very popular in the world, which uses commodity components and achieves good cost/performance ratio for parallel computing. However, it is very hard for the conventional cluster computers to extract its potential performance due to its large overhead hided in the network hardware. Considering the cluster’s characteristics, the optimization of communication is available.
Maestro project proposed Network Burst and Pipelined transfer as the optimization technique oriented to cluster’s inter-connection network. The Network Burst divides a message into a small data chunk (called packet) and sends it in burst as much packet at a transfer opportunity. On the other hand, the Pipelined transfer propagates the packets to the devices in the network one after another. These techniques has been implemented on an FPGA as Maestro Link Controller with the Maestro Link Protocol that implements the two techniques above. According to the experimental evaluation with MLC, two techniques proposed above was effective for the optimization of inter-cluster communication.
Network interface of Maestro Cluster Network
(64bit PCI@66MHz, IEEE1394 200Mbps PHY, PowerPC603e, 64MB EDO DRAM are embeded）
8port Switch Box of Maestro Cluster Network
(64bit PCI@66MHz, IEEE1394 200Mbps PHY, PowerPC603e, 64MB EDO DRAM are embeded)
Related papers
- Koichi Wada, Shinichi Yamagiwa and Munehiro Fukuda,”High Performance Network of PC Cluster Maestro,” Cluster Computing, Kluwer Academic Press, CLUS Vol. 5, No. 1, pp.33-42, 2002.
- 山際 伸一, 福田 宗弘, 和田 耕一, クラスタ向けネットワークアーキテクチャとプロトコルの提案-Maestroネットワークの開発と性能評価, 情報処理学会論文誌ハイパフォーマンスコンピューティングシステム, 2000年8月
- Shinichi Yamagiwa, Munehiro Fukuda, Koichi Wada, Design and Performance of Maestro Cluster Network, IEEE International Conference on Cluster Computing (CLUSTER2000), November 2000.
- Shinichi Yamagiwa, Masaaki Ono, Takeshi Yamazaki, Pusit Kulkasem, Masayuki Hirota, Koichi Wada, Maestro-Link: A High Performance Interconnect for PC Cluster, Lecture Note in Computer Science 1482 Field-Programmable Logic and Applications FPL98), pp.421-425,1998 August.
- 山際 伸一, 小野 雅晃, 和田 耕一, CPLDを用いたクラスタ・コンピューティング用IEEE1394ネットワークの開発, Altera PLD World ’98 技術論文集, pp191-198, 1998年10月
Maestro２ Project（２００２ - ）
Maestro２ Project（２００２ - ）
To improve the optimization techniques for Maestro project, Maestro2 project proposed continuous network burst transfer and out-of-order switching mechanism. The continuous network burst transfer improved the Network Burst technique to keep longer burst transfer at a transfer opportunity. On the other hand, the out-of-order switching mechanism implemented a concurrent message transfer with a shred bus on the switch box. In addition, Maestro2 Cluster Network has been implemented with MLX (Maestro Link Protocol dupleX), and was evaluated with several communication experiments. The communication is made by a special message passing software called MMP. According to the evaluations, the continuous network burst transfer and the out-of-order switching were effective to improve the inter-cluster communication.
Network interface of Maestro2 Cluster Network
(64bit PCI@66MHz, LVDS 600Mbps PHY, PowerPC603e, 64MB SDRAM are embeded）
8port Switch Box of Maestro2 Cluster Network
（64bit PCI@66MHz, LVDS 600Mbps PHY, PowerPC603e, 64MB SDRAM are embeded）
Related papers
- Keiichi aoki, Shinichi Yamagiwa, Koichi Wada and Masaaki Ono, Development and Evaluation of Message Passing Library for Maestro2 Cluster Network, Electronics and Computers in Japan, Part II, John Wiley & Sons,Inc., vol. 90, n. 11, pages 109-121, October 2007.
- Shinichi Yamagiwa, Kevin Ferreira, Keiichi Aoki, Masaaki Ono, Koichi Wada and Leonel Sousa, “Maestro2: Experimental evaluation of communication performance improvement techniques in the link layer“, Journal of Interconnection Networks (JOIN), World Scientific Publishing, vol.7 no.2, pp. 295-318, June 2006.
- 青木圭一, 山際伸一, 和田耕一, 小野雅晃, “Maestro2クラスタネットワーク向けメッセージパッシングライブラリの開発と評価“, 電子情報通信学会論文誌D, Vol. J89-D No.5 pp.919-931, 2006年5月.
- Kevin Ferreira, Shinichi Yamagiwa, Leonel Sousa, Keiichi Aoki , Koichi Wada, Luis Miguel Campos. Distributed Shared Memory System based on the Maestro2 High Performance Cluster Network. In 3rd International Symposium on Parallel and Distributed Computing (ISPDC 2004), 2004.
- Keiichi Aoki, Shinichi Yamagiwa, Kevin Ferreira, Luis Miguel Campos, Masaaki Ono, Koichi Wada, and Leonel Sousa, “Maestro2: High Speed Network Technology for High Performance Computing,” Proc. of the IEEE International Conference on Communications, June 2004.
- Shinichi Yamagiwa, Kevin Ferreira, Luis Miguel Campos, Keiichi Aoki, Masaaki Ono, Koichi Wada, Munehiro Fukuda, and Leonel Sousa, “On the Performance of Maestro2 High Performance Network Equipment, Using New Improvement Techniques,” Proc. of the 23rd IEEE International Performance Computing and Communications Conference, pp.103-110, April 2004.
- Keiichi Aoki, Shinichi Yamagiwa, Masaaki Ono, Koichi Wada and Luis Miguel Campos,”An Architecture of high performance cluster network: Maestro2,” Proc. of IEEE Pacific Rim Conf. on Communications, Computers and Signal Processing, pp. 784-787, Aug. 2003.